What Is RISC-V and Why It Will Be the next Big Thing for Wearables?

One of the most important components in a smartphone or any device for that matter is the System on a Chip, or as we say in general terms, a ‘processor’ or a CPU, in the case of personal computers. From Intel’s very first processor, the 4004, to one of the most popular processors of its time, the Intel 8006, there have been rapid developments in instruction set architecture, including both the CISC and RISC instruction sets used by Intel/ AMD and ARM. respectively. And now there’s a newcomer in town (well, RISC-V is quite old and was founded in 2010. However, it’s still relatively new compared to ARM). Here’s everything you need to know about RISC-V and why it’s so important not just for Android and WearOS, but also for Qualcomm and many other investors in the same.

What is RISC-V?

RISC-V, pronounced ‘risk five’, is an Instruction Set Architecture (ISA) like ARM and RISC, but unlike them it is completely license-free and open-source. To start, think of the instruction set architecture as a medium that connects hardware and software. It defines and dictates the way both hardware and software work to produce results, i.e. the outcome a user wants. It could be pressing a button in a user interface or passing complex instructions while playing a game.

RISC-V ISA is flexible and more efficient, and one of the main reasons why companies invest in it is because it is open-source and does not require licensing fees.

RISC-V What is it?

Given the name “RISC-V” you might consider it a kind of successor to RISC and no, that is not true. RISC is proprietary and used by ARM to issue instructions to companies such as Samsung, Qualcomm and Apple. They may use those ‘instructions’ to create their own SoCs. RISC-V, on the other hand, does not involve any intermediaries. It’s completely free and open source, meaning companies can follow the instructions without paying huge licensing fees, as they would with ARM, and start building a processor on the RISC-V ISA.

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Because the ISA is open source, like all open source software, RISC-V International is always looking for ways to improve the code and make it more efficient. Although one of the things worth mentioning is that RISC-V is license-free, but companies can use it and make it closed-source since they can. It’s more or less a similar situation to Android, where AOSP is completely free (although Google asks OEMs to pay licensing fees for Google Apps), but companies build on AOSP and don’t reveal the source code of their UI.


Both RISC and RISC-V are reduced instruction set computers found on devices with smaller SoCs such as smartphones, but the same has been extended to computers (M1 Macs, Qualcomm’s X Elite Platform) as well. CISC stands for Complex Instruction Set Computer and is used by processor manufacturers such as Intel and AMD.

The main difference between RISC-V, RISC and CISC is that RISC-V and RISC are Reduced Instruction Sets, with the former being completely free and open-source and the latter proprietary, while CISC is where the ISA completes complex instructions to solve an activity. In RISC, the ISA completes a large number of small instructions to complete a task.


An example of CISC is x86 and x86-64 from Intel and AMD. We’ll leave the explanation of their history for another article, but all you need to know is that x86 and x86-64 processors require more power and are not as efficient as RISC ISA, but are quite powerful. Although the line between RISC and CISC has blurred in recent years, CISC is still more widely used in personal computers and for industrial purposes than RISC; However, RISC is slowly approaching (Apple’s M1 processors, anyone?).

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Why RISC-V? What are the advantages?

One of the obvious benefits of RISC-V for companies like Google and Qualcomm is that it’s completely free and open source, so they don’t have to pay anything. By the way, here are a few benefits on the consumer side that will benefit both consumers and manufacturers.

  • Increased safety. Because it is open source, security flaws can be fixed very quickly.
  • Improved software updates as the ISA is common across manufacturers.
  • Better performance and efficiency of the SoCs thanks to the rapid development and improvements that come from being open source.
RISC V illustration

The other main reason we need RISC-V is to address ARM’s monopoly and future licensing issues. You see, ARM has recently started raising the prices of its licensing fees, leaving manufacturers with no choice but to pay the same since there’s nothing else for them to jump to. Another event that sent shockwaves through the industry was when NVIDIA tried to acquire ARM. This made the industry giants wonder if NVIDIA would stop licensing the ARM ISA to others, which, considering that it is NVIDIA, was very plausible. This led companies to invest in the development of RISC-V and lead the next generation of connected platforms by giving it a significant financial boost and boosting hardware development.

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Another important problem that RISC-V solves is related to trade barriers. If you work in the technology sector, you may have seen a lot of news in the US banning Huawei, and then China from doing the same, for whatever reason. RISC-V is completely free not only from the trade hurdles but also from the clutches of any country as it is based in Switzerland.

How will RISC-V benefit Google and Qualcomm?

Qualcomm to release new Arm-based chipset in 2023 to compete with Apple's M-series SoCs

Well, a lot of things. First, Qualcomm would not have to pay any fees and will likely move completely to RISC-V for all of its smartphone, IoT, and general connected technology products in the near future. At recent events, Qualcomm and Google will be working together to create RISC-V based processors for Google’s wearables (Pixel Watch and Fitbit) and hopefully for Pixels in the future (down with Tensor Google, please!). We think the processors will first appear in Google’s Fitbit range.

Pixel Watch 2 battery

Earlier this week, Google posted an update to Android on RISC-V and how the giant has been working to bring its WearOS and other platforms to RISC-V. The video in the post included booting and running Android on a RISC-V processor. Although AOSP (Android Open Source Project) is not yet fully optimized, Google claims that emulators will be available for public use by 2024.

Given the benefits of RISC-V, Google may push more updates (although 7 years on the Pixel 8 already seems excessive, but is great nonetheless) and improves the overall performance and battery life of the wearables. Part of the initial RISC-V vs. RISC test results look promisingbut RISC-V clearly still has a long way to go.

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